Input offset control
US9083232B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 23, 2014 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Feb 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45586
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Several circuits and methods for input offset control are disclosed. In an embodiment, a input offset control circuit includes a first input circuit and a second input circuit. The first input circuit is configured to operate within first common mode voltage range, configured to provide first input current, and configured to vary the first input current upon or subsequent to a variation of a voltage level in the first common mode voltage range. The second input circuit is coupled to the first input circuit and is configured to operate within second common mode voltage range, configured to provide a second input current, and configured to vary the second input current based on variation of the voltage level in the second common mode voltage range. Upon or subsequent to increasing the common mode voltage, the first input current is reduced and the second input current is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.