Patent · US Active

Semiconductor device and electronic device

US9083353B2 · kind B2 · utility

1Cited by

5References

12Claims

0Family size

Assignee

RENESAS ELECTRONICS CORPORATION · JP

Inventors

Hajime Sasaki · Tokyo, JP
Hirohiko Ito · Tokyo, JP
Shikiko Nachi · Tokyo, JP
Takanobu Naruse · Nishio, JP

Key dates

Filing date	Jul 27, 2013
Grant date	Jul 14, 2015
Priority date	—
Expiry date	Sep 18, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/18
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.