Signal multiplexing device
US9083476B2 · kind B2 · utility
1Cited by
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19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2012 |
| Grant date | Jul 14, 2015 |
| Priority date | — |
| Expiry date | Jul 24, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0276
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal multiplexing device includes a selector (1) that selects one of input data (4) and a complementary signal (16), a clock recovery circuit (30a) that adjusts the phase of a recovered clock (7) to the timing of the output signal of the selector (1), and a flip-flop circuit (3) that performs identification/recovery of the output signal of the selector (1) based on the recovered clock (7). The frequency of the complementary signal (16) is an integral submultiple of the frequency of the recovered clock (7). The selector (1) selects the complementary signal (16) during part of the no-signal period of the input data (4).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.