Patent · US Active

Semiconductor integrated circuit and method for designing the same

US9086451B2 · kind B2 · utility

1Cited by
1References
10Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 6, 2013
Grant dateJul 21, 2015
Priority date—
Expiry dateJan 14, 2034

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01R31/318566
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

A power-on self-test circuit and a pattern generation circuit are provided. The power-on self-test circuit includes a selection circuit and a comparator circuit. The selection circuit selects, instead of an external pin group corresponding to a test access port, an output of the pattern generation circuit when a self-diagnosis execution signal is asserted and supplies a test pattern generated by the pattern generation circuit to a built-in self-test circuit. The comparator circuit compares a test result of a circuit-under-test with an expected value. By asserting the self-diagnosis execution signal in this manner, the semiconductor integrated circuit mounted on a user system executes BIST.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.