Adjusting bit reliability information input for decoding stored data
US9086982B1 · kind B1 · utility
10Cited by
11References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 31, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Oct 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes systems and techniques relating to adjusting bit reliability information input for decoding data stored in a memory device. In some implementations, an apparatus, systems, or methods can include a memory controller that includes circuitry configured to receive data from a memory device, where the data includes at least first and second states; circuitry configured to compare a number of the first and second states of the received data; and circuitry configured to adjust a bit reliability information input to a decoder based, at least in part, on the comparison.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.