Patent · US Active

Programmable peripheral interconnect

US9087051B2 · kind B2 · utility

2Cited by

5References

32Claims

0Family size

Assignee

Nordic Semiconductor ASA · NO

Inventors

Junaid Elahi · Oslo, NO
Joar Olai Rusten · Trondheim, NO
Lasse Olsen · Trondheim, NO
Lars Sundell · Moss, NO

Key dates

Filing date	Dec 6, 2012
Grant date	Jul 21, 2015
Priority date	—
Expiry date	Dec 17, 2032

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Peripherals (18, 20, 22, 24, 26) are connected to a processor (6) and a programmable peripheral interconnect (10) is connected to each peripheral. One of the peripherals (18) is configured to signal an event to the interconnect, and one of the peripherals (20) is configured to respond to a task signal from the interconnect by performing a task. The task-receiving peripheral (20) has a task register (40), addressable by the processor (6), and performs the task in response to a change in the contents of the register (40). The interconnect (10) accesses a memory (14) in which a mapping is stored between an event of a first peripheral (18) and a task of a second peripheral (20), the mapping comprising (i) an identification of the event, and (ii) the address of a task register (40). The mapping causes the interconnect (10) to provide a channel by sending a task signal to the second peripheral (20) in response to a signal of the event from the first peripheral (18).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.