Simulation using parallel processors
US9087166B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2014 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Apr 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs-108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.