Semiconductor memory devices including a discharge circuit
US9087566B2 · kind B2 · utility
5Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Oct 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Semiconductor memory devices are provided. Each of the semiconductor memory devices may include first and second memory cells. The first memory cell may be connected to a bit line and a complementary bit line. Moreover, each of the semiconductor memory devices may include a discharge circuit connected to the first memory cell via the bit line and the complementary bit line. The discharge circuit may be configured to discharge the first memory cell during a read or write operation of the second memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.