Resistive memory arrangement and a method of forming the same
US9087975B2 · kind B2 · utility
3Cited by
0References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Jul 13, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S977/943
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
According to embodiments of the present invention, a resistive memory arrangement is provided. The resistive memory arrangement includes a nanowire, and a resistive memory cell including a resistive layer including a resistive changing material, wherein at least a section of the resistive layer is arranged covering at least a portion of a surface of the nanowire, and a conductive layer arranged on at least a part of the resistive layer. According to further embodiments of the present invention, a method of forming a resistive memory arrangement is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.