Low power current-voltage mixed ADC architecture
US9088295B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2013 |
| Grant date | Jul 21, 2015 |
| Priority date | — |
| Expiry date | Sep 14, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes systems and techniques relating to low power current-voltage mixed analog to digital converter (ADC) architecture. In some implementations, an ADC device includes a comparator array configured to receive an input analog voltage signal during a sample phase and a collection of reference voltages during a hold phase, a capacitor configured to receive the input analog voltage signal during the sample phase and to act as a feedback capacitor during the hold phase, an opamp coupled with the capacitor, and a transistor array configured to be powered by the opamp and activated by the comparator array to add or subtract currents to form a residue output voltage signal, which corresponds to the input analog voltage signal, used in analog to digital conversion of the input analog voltage signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.