Processors
US9092212B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Jun 11, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Sep 6, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing apparatus comprises a plurality of processors 12, each arranged to perform an instruction, and a bus 20 arranged to carry data and control tokens between the processors. Each processor 12 is arranged, if it receives a control token via the bus, to carry out the instruction, and on carrying out the instruction, to perform an operation on the data, to identify any of the processors 12 which are to be data target processors, and to transmit output data to any identified data target processors, to identify any of the processors which are to be control target processors, and to transmit a control token to any identified control target processors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.