Power failure tolerant cryptographic erase
US9092370B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/2143
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The various implementations described herein include systems, methods and/or devices used to enable power failure tolerant cryptographic erasure in a storage device having a first encryption key established as a current encryption key. The method includes performing a set of first stage operations including selecting first and second sets of memory blocks and obtaining a second encryption key. The method includes performing a set of second stage operations including storing, in the first set of memory blocks, first and second sets of metadata, encrypted using the second encryption key. The method includes performing a set of third stage operations, including storing, in the second set of memory blocks, the second set of metadata encrypted using the second encryption key. The method includes setting the second encryption key as the current encryption key for the plurality of memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.