Integrated circuit design flow with device array layout generation
US9092589B2 · kind B2 · utility
5Cited by
12References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 28, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Feb 28, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2111/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for designing an integrated circuit generates a schematic of the integrated circuit based on a set of system design rule constraints. The system also receives a proposed device array layout from a device array design module. The device array design module is configured to generate the proposed device array layout free from the set of system design rule constraints. The system further generates a revised schematic of the integrated circuit including the proposed device array layout. The system additionally determines if the revised schematic violates one or more of the system design rule constraints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.