Power-efficient sensory recognition processor
US9092672B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Nov 19, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention provides a computer and/or processor architecture optimized for power-efficient computation of a class of sensory recognition (e.g. vision) algorithms on a single computer chip derived from research into how humans process sensory information, such as vision. The processor for efficiently recognizing sensory information with recognizable features defines a feature recognition engine that resolves features from the sensory information and provides a feature information input. A plurality of processing nodes, arranged in a hierarchy of layers, receives the input and, in parallel, recognizes multiple components of the features. Recognized features are transferred between the layers so as to build likely recognition candidates and remove unlikely recognition candidates. A memory in each of the nodes refreshes and retains predetermined features related to likely recognition candidates as the features are transferred between the layers. A thresholding process determines when at least one of the recognition candidates sufficiently matches predetermined criteria.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.