Buffer for ordering out-of-order data, and corresponding integrated circuit and method for managing a buffer
US9093133B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Dec 30, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/123
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer for ordering out-of-order data includes a memory with a plurality of memory locations for temporarily storing data and a detection circuit configured for generating a control signal when the memory locations contain valid data. The detection circuit includes a first block configured for generating validity signals that identify the memory locations containing valid data and a search circuit configured for determining a search pointer as a function of the validity signals. In the case where each memory location contains valid data, the search pointer indicates the last memory location. In the case where at least one memory location is still free, the search pointer indicates the first memory location that is free.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.