Semiconductor device and fabrication method
US9093317B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 30, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Mar 30, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
Abstract
Semiconductor devices and fabrication methods are provided. A semiconductor substrate includes a first region and a second region. A gate dielectric material layer is formed to cover the first region, and a control gate dielectric layer is formed over a surface portion of the second region. The control gate dielectric layer has a top surface higher than the gate dielectric layer. A gate material layer is conformally formed to cover an entire surface of the semiconductor substrate and has a top surface in the second region higher than a top surface in the first region. A first filling material layer is formed on the gate material layer. A first patterned mask layer is formed on the first filling material layer to form a gate on a gate dielectric layer in the first region. A control gate is formed on the control gate dielectric layer of the second region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.