Impedance calibration in a driver circuit and a receiver circuit
US9094000B1 · kind B1 · utility
1Cited by
5References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Feb 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Some of the embodiments of the present disclosure provide an integrated circuit communicating with a device over a multi-pin parallel bus, the integrated circuit comprising: at least a first pin and a second pin to communicate with the device over the multi-pin parallel bus; and an impedance tuning module disposed in the integrated circuit and configured to tune an impedance value of a first impedance associated the first pin separately from tuning an impedance value of a second impedance associated with the second pin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.