Single component sleep-convention logic (SCL) modules

US9094013B2 · kind B2 · utility

Assignees

• THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ARKANSAS · US
• NANOWATT DESIGN, LLC · US

Inventors

• Scott Christopher Smith · Chesterfield, US
• Jia Di · Fayetteville, US
• Jerry Frenkil · Concord, US
• Aaron Arthurs · Springdale, US
• Ron Foster · Fayetteville, US

Key dates

• Filing date: May 24, 2013
• Grant date: Jul 28, 2015
• Expiry date: Oct 10, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03K19/173
• WIPO field: Basic communication processes
• WIPO sector: Electrical engineering

Abstract

A multi-rail module having mutually exclusive outputs. The module includes first and second-rail logic circuits, first and second-rail driver circuits, and a PMOS transistor sourcing VDD to both the first and second driver circuits. The first-rail logic circuit is coupled to VDD and ground and has a first logic input and a first logic output. The second-rail logic circuit is coupled to VDD and ground and has a second logic input and a second logic output. The first-rail driver circuit is coupled to ground, receives the first logic output, and has a first-rail output Q1. The second-rail driver circuit is coupled to ground, receives the second logic output, and has a second-rail output Q0. The PMOS transistor has a gate driven by a SLEEP signal.