DAC current source matrix patterns with gradient error cancellation
US9094042B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2013 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Aug 9, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/747
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
First order gradient errors are canceled with no current source splitting by placing consecutive current sources symmetrically around the center of the array. Consecutive elements that correspond to small input amplitudes (mid-scale codes) make a smaller spatial jump than those correspond to larger signal amplitudes. Both linear and second order gradients are reduced by splitting each current cell into two and placing sub-elements symmetrically with respect to the center of the array to address the linear gradient effect. To address second order gradients, current element placement follows a pattern such that consecutive element pairs are chosen with one of the pair being placed with respect to the zero error contour of the second order gradient so as to have a positive error and the second of the pair being placed so as to have a negative error resulting in reduced second order error accumulation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.