Transceiver architecture with improved capacity and interference mitigation
US9094114B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2014 |
| Grant date | Jul 28, 2015 |
| Priority date | — |
| Expiry date | Nov 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/6418
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A transceiver having substantially improved capacity and interference mitigation. The transceiver comprises a first direct conversion receiver (DCR) and a plurality of additional DCRs, each of the plurality of additional DCRs having essentially identical constituent components to the first DCR. Each DCR does a direct down-conversion from RF to a complex pair of baseband I and Q components. The complex signal pair from each DCR is digitized and further processed in a modem module where the signal is optimally filtered, demodulated, and error-corrected. The modem module reconstructs the message information contained in each signal from all of the DCR's, simultaneously providing the demodulated data that was contained in the RF signals. The dynamic range of the system is extremely large (i.e., approximately 80 dB).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.