Secure digital input/output low-power mode
US9098259B1 · kind B1 · utility
4Cited by
5References
23Claims
0Family size
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Key dates
| Filing date | May 26, 2011 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jun 4, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-power mode for interfaces, such as secure digital input/output (SDIO) interfaces, is described. The low-power mode provides significant power savings while allowing rapid resumption of data transfer on the interface. The SDIO low-power mode gates an SDIO clock and transitions the SDIO bus to a 1-bit mode. One line of the bus carries the 1-bit data while another line carries interrupts from an SDIO peripheral. Normal data transmission results in enabling the SDIO clock and setting the bus set to the 4-bit mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.