Transactional memory that performs a direct 24-BIT lookup operation
US9098264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Aug 18, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A transactional memory (TM) receives a lookup command across a bus from a processor. Only final result values are stored in memory. The command includes a base address, a starting bit position, and mask size. In response to the lookup command, the TM pulls an input value (IV). A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV and the base address are used to generate a memory address. The memory address is used to read a word containing multiple result values (RVs) from memory. One RV from the word is selected using a multiplexing circuit and a result location value (RLV) generated from the portion of the IV. A word selector circuit and arithmetic circuits are used to generate the memory address and RLV. The TM sends the selected RV to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.