Multi-core processor system, computer product, and control method
US9098414B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Aug 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-core processor system includes shared memory shared by cores of a multi-core processor; first cache memories respectively for each of the cores; a second cache memory between the shared memory and the first cache memories, and storing shared data shared by the cores and referred to by at least threads executed by the multi-core processor; a reading unit that reads a value of a given variable from the shared memory; a determining unit that based on a read request for the given variable, determines whether the given variable is shared data or non-shared data that is referred to by only one thread; and a transferring unit that, when the given variable is determined as non-shared data, transfers without using the second cache memory, the value of the given variable to a first cache memory of a core that is a request origin of the read request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.