Scalable architecture for testing wireless devices
US9098485B2 · kind B2 · utility
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3References
14Claims
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Key dates
| Filing date | Apr 13, 2009 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Apr 28, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2822
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A simulator for testing a wireless device includes at least one module capable of being connected with other modules. Each simulator module includes first and second sets of ports, combiners and a channel emulator. Each combiner provides a low insertion loss pathway between a common port and first and second ports of the combiner, and isolation between the first port and the second port of the combiner. The combiners allow interconnection of multiple modules, thereby scaling the number of devices that can be tested by the simulator at a given time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.