Display and automatic improvement of timing and area in a network-on-chip
US9098658B2 · kind B2 · utility
0Cited by
2References
14Claims
0Family size
Assignee
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Key dates
| Filing date | May 21, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | May 21, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and NoC design tool is disclosed that automatically maps the paths listed in a timing report and the unit size in an area report to the topology of a NoC and displays the paths and unit sizes in a GUI. The tool can also automatically add pipeline stages, separated by the maximum delay allowed in the timing budget, in order to achieve timing closure in an automated way.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.