Semiconductor storage device
US9099177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jul 25, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
With the aim of providing a semiconductor memory device being suitable for miniaturization and allowing a contact resistance to lower, the wiring structure of a memory array (MA) is formed as follows. That is, word lines (2) and bit lines (3) are extended in parallel to each other, each of the word lines is bundled with another word line, each of the bit lines is bundled with another bit line, and two bit lines formed vertically over respective bundled two word lines are separated electrically. Such a configuration makes it possible to: form a larger contact at a bundling section (MLC) of wires; and lower a contact resistance in the memory array suitable for miniaturization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.