Erase algorithm for flash memory
US9099192B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2014 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Feb 4, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile memory device includes a sector pass/fail indicator circuit configured to store a pass/fail indicator for each sector in a first block of memory cells. The pass/fail indicator has a first value indicating the respective sector has failed erase verification and has a second value indicating the respective sector has passed erase verification. The sector pass/fail indicator circuit set the respective pass/fail indicators to the second value for one or more sectors in the first block after the respective sectors pass erase verification following a previous block erase operation of the first block. The first block is subjected to subsequent block erase operation where only word lines associated with the sectors having a pass/fail indicator having the first value are biased to the first bias voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.