Method of manufacturing semiconductor device and semiconductor device
US9099334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2013 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improvement is achieved in the manufacturing yield of a semiconductor device including a plurality of field effect transistors having different characteristics over the same substrate. By combining anisotropic dry etching with isotropic wet etching or isotropic dry etching, three types of sidewalls having different sidewall lengths are formed. By reducing the number of anisotropic dry etching steps, in a third n-type MISFET region and a third p-type MISFET region where layout densities are high, it is possible to prevent a semiconductor substrate from being partially cut between n-type gate electrodes adjacent to each other, between the n-type gate electrode and a p-type gate electrode adjacent to each other, and the p-type gate electrodes adjacent to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.