Charge ordered vertical transistors

US9099384B2 · kind B2 · utility

Assignees

• DREXEL UNIVERSITY · US
• The Trustees of the University of Pennsylvania · US

Inventors

• Steven J. May · Minnetonka, US
• Jonathan E. Spanier · Yeadon, US
• James Rondinelli · Chicago, US
• Mitra Lenore Taheri · Philadelphia, US
• Robert C. Devlin · Concord, US
• Andrew M. Rappe · Levittown, US

Key dates

• Filing date: Feb 15, 2013
• Grant date: Aug 4, 2015
• Expiry date: Feb 15, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N99/03

Abstract

A vertical charge ordered transistor is disclosed. A thin charge ordered layer is employed as a tunnel barrier between two electrodes. A gate-induced accumulation of charge destabilizes the charge ordered state around the circumference of the device, opening up a parallel ohmic conduction channel, which leads to an exponential increase in source-drain current. VCOT devices have the potential to exhibit very large on/off ratios, low off-state currents, and sub-threshold slopes below 60 mV/dec.