Methods of forming fine patterns for semiconductor devices
US9099399B2 · kind B2 · utility
6Cited by
8References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2014 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Aug 25, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/20
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming fine patterns for semiconductor devices are provided. A method may include sequentially forming a lower layer and a mask layer having first openings on a substrate, forming pillars to fill the first openings and protrude upward from a top surface of the mask layer, forming a block copolymer layer on the substrate with the pillars, performing a thermal treatment to the block copolymer layer to form a first block portion and second block portions, removing the second block portions to form guide openings exposing the mask layer, and etching the mask layer exposed by the guide openings to form second openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.