Integrated driver and related method
US9099965B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2011 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | May 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30132
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A driver circuit may include a first node (VA), and a first circuit to generate on the first node (VA) an inverted replica of an input signal (VIN) during driver switching between a first supply voltage (Vdd1) and ground, the inverted replica having a threshold voltage value based upon a reference voltage (Vref) greater than the first supply voltage (Vdd1). The driver circuit may include a cascode stage (M3) to be controlled by the reference voltage (Vref) and to be coupled between a second supply voltage (Vdd2) and the first node, a delay circuit (D) to generate a delayed replica of the input signal (VIN), an amplifier, and a switching network (M5, M6) to couple a control terminal of an active load transistor (M9) either to one of the reference voltage (Vref) or to ground, based upon the input signal (VIN).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.