Global synchronous clock circuit and method for blade processors

US9104343B2 · kind B2 · utility

Assignee

• SILICON GRAPHICS INTERNATIONAL CORP. · US

Inventors

• Rodney Ruesch · Eau Claire, US
• Eric C. Fromm · Chippewa Falls, US
• Robert W. Cutler · Chippewa Falls, US
• Richard G. Finstad · Eau Claire, US
• Dale R. Purdy · Apple Valley, US
• Brian J. Johnson · Rosemount, US
• John F. Steiner · Mendota Heights, US

Key dates

• Filing date: Mar 13, 2013
• Grant date: Aug 11, 2015
• Expiry date: Dec 18, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04J3/0661
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Processor clock signals are generated for each processor in a HPC system, such that all the processor clock signals are of the same frequency. Furthermore, as part of a startup (boot) procedure, a process sets all time stamp counters (TSCs) of the processors, such they indicate identical times. Each blade of the HPC system recovers a recovered clock signal from a synchronous communication network, to which the blade is coupled. The blade generates a processor clock from the recovered clock signal and provides the processor clock to processor(s) on the blade. Each chassis is coupled to a second, system-wide, synchronous communication network, and each chassis synchronizes its chassis synchronous communication network with the system-wide synchronous communication system. Thus, all the processor clock signals are generated with the same frequency.