System and method for controlling central processing unit power with guaranteed transient deadlines
US9104411B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2012 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Aug 22, 2033 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees to ensure that a processor does not remain in a busy state (e.g., due to transient workloads) for more than a predetermined amount of time above that which is required for that processor to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of a processor based on a variable delay to ensure that the processing core only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.