Multi-function floating point unit
US9104510B1 · kind B1 · utility
27Cited by
8References
19Claims
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Key dates
| Filing date | Apr 30, 2010 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Dec 13, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arithmetic units and methods for floating point processing are provided. In exemplary embodiments, data paths to and from multiple multipliers and adders are flexibly combined through crossbars and alignment units to allow a wide range of mathematical operations, including affine and SIMD operations. The micro-architecture for a high-performance flexible vector floating point arithmetic unit is provided, which can perform a single-cycle throughput complex multiply-and-accumulate operation, as well as a Fast Fourier Transform (radix-2 decimation-in-time) Butterfly operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.