Reduced-impact error recovery in multi-core storage-system components
US9104575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 18, 2012 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Mar 20, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for recovering from an error in a multi-core storage-system component is disclosed. In one embodiment, such a method includes detecting an error in a first core of a multi-core component. The method determines whether the error was one of (1) detected by the first core; and (2) detected by a core other than the first core. In the event the error was detected by the first core and the error is recoverable, the first core recovers from the error without substantially impacting operation of other cores in the multi-core component. In the event the error was detected by a core other than the first core and the error is recoverable, a core other than the first core recovers from the error without substantially impacting operation of other cores in the multi-core component. A corresponding apparatus and computer program product are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.