Information processing apparatus, system time synchronization method and computer readable medium
US9104609B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 18, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Aug 1, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The time in the chipset of backup resources is synchronized easily at the system time.An information processing apparatus including: an operational chipset which includes a first Real Time Clock (RTC); a backup chipset which includes a second RTC: a third RTC which times system time; a difference time calculation unit which calculates a difference time between a system time periodically notified of from the first RTC of the operational chipset and the system time which the third RTC times; a holding unit which holds the difference time; a calculation unit which calculates a temporary system time which is set to the second RTC of the backup chipset to which a chipset switching operated, based on the system time of the third RTC and the difference time at the time of the chipset switching; and a configuration unit which sets the temporary system time to the second RTC of the backup chipset.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.