Hardware for performing arithmetic operations
US9104633B2 · kind B2 · utility
29Cited by
2References
60Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 7, 2011 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Oct 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3001
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware for performing sequences of arithmetic operations. The hardware comprises a scheduler operable to generate a schedule of instructions from a bitmap denoting whether an entry in a matrix is zero or not. An arithmetic circuit is provided which is configured to perform arithmetic operations on the matrix in accordance with the schedule.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.