Multi-core geometry processing in a tile based rendering system
US9105131B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 5, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Aug 5, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T11/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and an apparatus are provided for combining multiple independent tile-based graphic cores. A block of geometry, containing a plurality of triangles, is split into sub-portions and sent to different geometry processing units. Each geometry processing unit generates a separate tiled geometry list that contains interleave markers that indicate an end to a sub-portion of a block of geometry overlapping a particular tile, processed by that geometry processing unit, and an end marker that identifies an end to all geometry processed for a particular tile by that geometry processing unit. The interleave markers are used to control an order of presentation of geometry to a hidden surface removal unit for a particular tile, and the end markers are used to control when the tile reference lists, for a particular tile, have been completely traversed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.