Dummy cell array for fin field-effect transistor device and semiconductor integrated circuit including the dummy cell array
US9105467B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 16, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Sep 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A semiconductor device includes a substrate; a device area of the substrate, the device area including a plurality of device unit cells; and a dummy cell array arranged around the device area. The dummy cell array includes a plurality of dummy unit cells repeatedly arranged in a first direction and a second direction perpendicular to the first direction, each of the dummy cell unit having a structure corresponding to a device unit cell. The device unit cell includes at least a first transistor in the device area. The structure of the dummy unit cell includes an active area and a gate line. For each dummy unit cell, the active area and the gate line extend beyond a cell boundary that defines the dummy unit cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.