ESD protection structure and ESD protection circuit

US9105477B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Paul Ouyang · Shanghai, CN
• Wenjun Weng · Shanghai, CN
• Huijuan Cheng · Shanghai, CN
• Jie Chen · Shanghai, CN
• Hongwei Li · Burnaby, CA

Key dates

• Filing date: Mar 27, 2014
• Grant date: Aug 11, 2015
• Expiry date: Mar 27, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/815

Abstract

An electrostatic discharge (ESD) protection structure and an ESD protection circuit are provided. A PMOS transistor is located in a first region of a first N-type well region of a semiconductor substrate. A first doped base region located in a second region of a first N-type well region is N-type doped and connected to an external trigger-voltage adjustment circuit. An NMOS transistor is located in a third region of a first P-type well region. A second doped base region located in the fourth region of the first P-type well region is P-type doped and connected to the external trigger-voltage adjustment circuit. The external trigger-voltage adjustment circuit can be configured to pull up an electric potential of the second doped base region when the power supply terminal generates an instantaneous electric potential difference.