Reduced gain variation biasing for short channel devices
US9106186B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 2, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | May 2, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/555
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An amplifier biasing circuit that reduces gain variation in short channel amplifiers, an amplifier biasing circuit that produces a constant Gm biasing signal for short channel amplifiers, and a multistage amplifier that advantageously incorporates embodiment of both types of amplifier biasing circuits are described. Both amplifier biasing circuit approaches use an operational amplifier to equalize internal bias circuit voltages. The constant Gm biasing circuit produces a Gm of 1/R, where R is the value of a trim variable resistor value. The biasing circuit that reduces gain variation produces a Gm of approximately 1/R, where R is the value of a trim variable resistor value, however, the biasing circuit is configurable to adjust the bias circuit Gm to mitigate the impact of a wide range of circuit specific characteristics and a wide range of changes in the operational environment in which the circuit can be used, such as changes in temperature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.