Impedance calibration circuit and method
US9106219B2 · kind B2 · utility
4Cited by
9References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Nov 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An embodiment includes an impedance calibration circuit having a calibrator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit and to generate an output based on the comparison. The calibrator further includes respective filters coupled between the external node and a first input of the comparator, and between the internal node and a second input of the comparator. The filters are configured for symmetric noise injection into the comparator from a chip ground line to which a programmable resistor at the internal node is coupled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.