Spread-spectrum phase locked loop circuit and method
US9106236B2 · kind B2 · utility
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3References
7Claims
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Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/7087
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase locked loop (PLL) circuit and a method thereof are provided. In an embodiment, the PLL circuit includes: a switched capacitor circuit, in which the switched capacitor circuit generates a modulation waveform, and the modulation waveform is injected into the PLL circuit in a current form, so that a PLL output frequency is modulated. Compared with the spread spectrum phase locked loop (SS-PLL) in the prior art, the SS-PLL in embodiments of the present invention is simple in structure, low in power consumption, low in silicon overhead, and flexible both in spreading factor and modulation frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.