Successive approximation register analog-to-digital converter and associated control method
US9106246B2 · kind B2 · utility
9Cited by
4References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 22, 2014 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Dec 22, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/468
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a successive approximation register analog-to-digital converter (SAR ADC), where a high bit capacitor of the SAR ADC is composed of a plurality of sub-capacitors, and these sub-capacitors are calibrated when the SAR ADC is working. Therefore, the working speed of the SAR ADC will not be influenced. In addition, a capacitance of each sub-capacitor is lower than a redundant capacitance of the SAR ADC, therefore, input signals of the SAR ADC are allowed to have full swing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.