Patent · US Active

Memory efficient implementation of LDPC decoder

US9106262B2 · kind B2 · utility

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14Claims

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Assignee

Hong Kong Applied Science and Technology Research Institute Company Limited · CN

Inventors

Felix Chow · San Jose, US
Chun Hang Lee · Sha Tin, CN

Key dates

Filing date	Mar 24, 2014
Grant date	Aug 11, 2015
Priority date	—
Expiry date	Mar 24, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH03M13/2906
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A computer processor implementable method of decoding low-density parity-check (LDPC) code, comprising: receiving a log-likelihood-ratio (LLR) input bitstream; performing a combined bit-deinterleaving and reordering process on the LLR input bitstream and storing in a physical memory space, comprising: determining a logical memory address for each LLR bit in the LLR input bitstream, determining a physical memory address for each LLR bit in the LLR input bitstream from logical memory address of the LLR bit; decoding the LLR input bitstream stored in the physical memory space; and performing a combined de-reordering and de-mapping process on the decoded LLR input bitstream.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.