Flip-flop circuit having a reduced hold time requirement for a scan input
US9110141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2012 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Jul 4, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318555
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scan flip-flop circuit comprises a scan input sub-circuit and a selection sub-circuit. The scan input sub-circuit is configured to receive a scan input signal and a scan enable signal and, when the scan enable signal is activated, generate complementary scan input signals representing the scan input signal that are delayed relative to a transition of a clock input signal between two different logic levels. The selection sub-circuit is coupled to the scan input sub-circuit and configured to receive the complementary scan input signals and, based on the scan enable signal, output an inverted version of either the scan input signal or a data signal as a first selected input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.