Throttling integrated link
US9110666B2 · kind B2 · utility
0Cited by
20References
19Claims
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Key dates
| Filing date | Mar 4, 2011 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Sep 19, 2031 |
Classification
- Technology area (CPC —)General
Abstract
Methods and apparatus for throttling an interface that is integrated on the same die as a processor are described. In one embodiment, a signal from an Integrated Input/Output hub (e.g., integrated on the same die as a processor) causes throttling of a link coupled between the IIO and an Input/Output (IO) device. Other embodiments are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.