Method, controller, and memory device for correcting data bit(s) of at least one cell of flash memory
US9110824B2 · kind B2 · utility
2Cited by
5References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 7, 2013 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Aug 29, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for correcting data bit of at least a cell of a flash memory includes: determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate a first determination result; and, correcting/modifying the data bit corresponding to the electric potential of the first cell according to the first determination result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.