Generation of simulated errors for high-level system validation
US9110879B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 24, 2014 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Mar 24, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3696
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device, integrated circuit and method for generating simulated errors are disclosed. In the disclosed device, integrated circuit and method, an original data value is read from a memory. The original data value is intercepted by the integrated circuit. The integrated circuit is operable to virtualize an error in the original data value to generate a modified data value. The integrated circuit is also operable to generate an interrupt according to the virtualization. This disclosure may be particularly useful for high-level memory validation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.