Pipelined L2 cache for memory transfers for a video processor
US9111368B1 · kind B1 · utility
2Cited by
151References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2005 |
| Grant date | Aug 18, 2015 |
| Priority date | — |
| Expiry date | Mar 1, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/86
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for using a pipelined L2 cache to implement memory transfers for a video processor. The method includes accessing a queue of read requests from a video processor. For each of the read requests, a determination is made as to whether there is a cache line hit corresponding to the request. For each cache line miss, a cache line slot is allocated to store a new cache line responsive to the cache line miss. An in-order set of cache lines is output to the video processor responsive to the queue of read requests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.